1. Field of the Invention
The invention relates in general to a method for fabricating a semiconductor structure, and more particularly to a method for forming an inter-metal dielectric layer.
2. Description of the Related Art
Inter-metal dielectric layers are generally used to separate and electrically isolate wiring lines and other conductors in semiconductor circuit devices. Such devices may include multiple layers of wiring lines and other conductors and require isolation between adjacent conducting structures and isolation between layers. As device are being scaled down to smaller geometries, the gaps between wiring lines generally have higher aspect ratios (ratio of height to width), which are harder to fill than small aspect ratio gaps. In addition, as the distance between wiring lines and other conductors becomes smaller, capacitive coupling between wiring lines and other conductors becomes a limitation on the speed of the integrated circuit device. For adequate device performance in reduced dimension devices, it is necessary for the dielectric provided between wiring lines to meet a number of requirements. The dielectric material should be able to completely fill the gap between conductors and should be planarizable so that successive layers can be deposited and processed. The dielectric material should also be resistant to moisture transport and have a low dielectric constant to minimize wiring capacitance between conductors and between layers.
It is extremely important to deposit a high quality, substantially void-free dielectric that can fill the small, high-aspect ratio gaps between wiring lines. Dielectric layers for wiring line isolation are often formed by chemical vapor deposition (CVD) processes which deposit material onto a surface by transporting certain gaseous precursors to the surface and causing the precursors to react at the surface. High density plasma chemical vapor deposition (HDPCVD) allows for the addition of a sputtering component to a plasma deposition process which can be controlled to promote gap-filling during deposition processes in a manner superior to conventional CVD processes. HDPCVD deposits a dielectric layer having superior density, moisture resistance and planarization properties as compared to conventional CVD dielectric layers. The bias sputtering component of HDPCVD derives from the introduction of an accelerating potential between the plasma-excited deposition gases and the deposition substrate. The ions accelerated by the bias sputtering component of HDPCVD processes etch the material present on the surface of the deposition substrate and sputter the etched material, generally to further recessed portions on the substrate. As an oxide is deposited onto the surface of a substrate by HDPCVD incorporating bias sputtering, the oxide is also etched from the surface of the substrate and sputtered into recessed portions of the substrate. As such, those portions of a deposited layer that are closest to a gap are the most likely to be etched and sputtered into the gap. This produces the well-known surface faceting of the HDPCVD process and the ability of the process to fill gaps effectively.
HDPCVD processes may accomplish both deposition and etching at the same time, depending on the level of a bias sputtering component chosen for the deposition environment during the process. Bias sputtering removes and redistributes dielectric material from wiring line sidewalls, enables substantially void-free filling of gaps and enhances planarization. As described above, the sputtering component acts to prevent material build-up at the corners of the wiring lines and results in better gap-filling.
In another aspect, as line width of a semiconductor device is reduced, the distance between two conductive layers is accordingly reduced, causing a more severe parasitic-capacitor effect. The dielectric constant (K) quantity of an inter-metal dielectric (IMD) layer between the conductive layers becomes an essential parameter. If the K quantity becomes high, the parasitic-capacitor effect becomes more severe. A large parasitic-capacitor effect may cause a large resistance-capacitance (RC) time delay (RC delay), resulting in a decrease of the operation speed of the device. Therefore, a faster operation speed can be achieved by reducing the K quantity of the IMD layer.
A conventional method provides a fluorinated silicon glass (FSG) film as an IMD layer over wiring lines using HDPCVD to decrease the dielectric constant of the IMD layer. The FSG film formed by HDPCVD is applied to fill a high aspect ratio gap. A silicon oxide layer is formed on the FSG film by plasma-enhanced CVD (PECVD) to provide a dielectric layer with a sufficient thickness. A chemical mechanical polishing (CMP) process is performed to remove a part of the silicon oxide layer. A planarized surface is thus obtained.
In order to fill high aspect ratio gaps between the wiring lines, an FSG film is deposited with a thickness that is about 1.2 times a thickness of the wiring lines. The thick FSG film is easily exposed while performing the CMP process. F atoms contained in the FSG film react with H.sub.2 O in a slurry used in the CMP process and form hydrogen fluoride (HF). HF may erode metal used as a contact or an interconnect structure in subsequent steps.
However, the thickness of the FSG film is limited to avoid eroding metal. The thin FSG film cannot fully fill the gaps between the wiring lines. A thick PECVD silicon oxide layer is formed on the thin FSG film to achieve a predetermined thickness. But the PECVD silicon oxide layer results in worse gap-filling so that voids form in the small gaps between the wiring lines.